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Move the power ground ring from TM1+TM2 to M5+TM1. The connection
between the IO ring and PGR will be estabilished with strips on TM2.
When the PGR is using TM2, it won't have any connection to the IO
cells on the north and south side because the connection strips won't
need vias to connect to the PGR.
Also increase the power strips width for the chip-level and macro
power distribution netweek. Additionally, decrease the pitch and
offset.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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