Merge pull request #730 from ckormanyos/better_name_esp32p4

Handle #729 via better name esp32p4 riscv soc

Author: ckormanyos

.github/workflows/real-time-cpp.yml

@@ -236,7 +236,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        suite: [ bl602_sifive_e24_riscv, riscvfe310, wch_ch32v307, xtensa_esp32_p4, xtensa_esp32_s3_riscv_cop ]
+        suite: [ bl602_sifive_e24_riscv, esp32p4_riscv_soc, riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ]
     steps:
       - uses: actions/checkout@v4
         with:

readme.md

@@ -75,6 +75,7 @@ The reference application supports the following targets (in alpha-numeric order
 | `bcm2835_raspi_b`                      | RaspberryPi(R) Zero with ARM1176-JZFS(TM)                   | X             |
 | `bl602_sifive_e24_riscv`               | BL602 single-core RISC-V (SiFive E24)                       | X             |
 | `Debug`/`Release`                      | PC on `Win*` via MSVC x64 compiler `Debug`/`Release`        |               |
+| `esp32p4_riscv_soc`                    | Espressif ESP32-P4 multicore RISC-V SoC                     | X             |
 | `host`                                 | PC/Workstation on `Win*`/`mingw64`/`*nix` via host compiler |               |
 | `lpc11c24`                             | NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+          |               |
 | `nxp_imxrt1062`                        | Teensy 4.0 Board / NXP(R) iMXRT1062 ARM(R) Cortex(R)-M7     | X             |
@@ -96,7 +97,6 @@ The reference application supports the following targets (in alpha-numeric order
 | `wch_ch32v307`                         | WCH CH32v307 RISC-V board                                   |               |
 | `wch_ch32v307_llvm`                    | WCH CH32v307 RISC-V board (but using an LLVM toolchain)     |               |
 | `x86_64-w64-mingw32`                   | PC on `Win*`/`mingw64` via GNU/GCC x86_x64 compiler         |               |
-| `xtensa_esp32_p4`                      | Espressif (XTENSA) ESP32-P4 multicore RISC-V SoC            | X             |
 | `xtensa_esp32_s3`                      | Espressif (XTENSA) NodeMCU ESP32-S3                         | X             |
 | `xtensa32`                             | Espressif (XTENSA) NodeMCU ESP32                            | X             |
 

ref_app/ref_app.sln

@@ -53,6 +53,7 @@ Global
 		target avr|x64 = target avr|x64
 		target bcm2835_raspi_b|x64 = target bcm2835_raspi_b|x64
 		target bl602_sifive_e24_riscv|x64 = target bl602_sifive_e24_riscv|x64
+		target esp32p4_riscv_soc|x64 = target esp32p4_riscv_soc|x64
 		target lpc11c24|x64 = target lpc11c24|x64
 		target nxp_imxrt1062|x64 = target nxp_imxrt1062|x64
 		target r7fa4m1ab|x64 = target r7fa4m1ab|x64
@@ -73,7 +74,6 @@ Global
 		target wch_ch32v307_llvm|x64 = target wch_ch32v307_llvm|x64
 		target wch_ch32v307|x64 = target wch_ch32v307|x64
 		target x86_64-w64-mingw32|x64 = target x86_64-w64-mingw32|x64
-		target xtensa_esp32_p4|x64 = target xtensa_esp32_p4|x64
 		target xtensa_esp32_s3_riscv_cop|x64 = target xtensa_esp32_s3_riscv_cop|x64
 		target xtensa_esp32_s3|x64 = target xtensa_esp32_s3|x64
 		target xtensa32|x64 = target xtensa32|x64
@@ -90,6 +90,7 @@ Global
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target avr|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target bcm2835_raspi_b|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target bl602_sifive_e24_riscv|x64.ActiveCfg = Release|x64
+		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target esp32p4_riscv_soc|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target lpc11c24|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target nxp_imxrt1062|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target r7fa4m1ab|x64.ActiveCfg = Release|x64
@@ -110,7 +111,6 @@ Global
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307_llvm|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target x86_64-w64-mingw32|x64.ActiveCfg = Release|x64
-		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_p4|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3|x64.ActiveCfg = Release|x64
 		{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa32|x64.ActiveCfg = Release|x64
@@ -130,6 +130,8 @@ Global
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bcm2835_raspi_b|x64.Build.0 = target bcm2835_raspi_b|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bl602_sifive_e24_riscv|x64.ActiveCfg = target bl602_sifive_e24_riscv|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bl602_sifive_e24_riscv|x64.Build.0 = target bl602_sifive_e24_riscv|x64
+		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target esp32p4_riscv_soc|x64.ActiveCfg = target esp32p4_riscv_soc|x64
+		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target esp32p4_riscv_soc|x64.Build.0 = target esp32p4_riscv_soc|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target lpc11c24|x64.ActiveCfg = target lpc11c24|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target lpc11c24|x64.Build.0 = target lpc11c24|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target nxp_imxrt1062|x64.ActiveCfg = target nxp_imxrt1062|x64
@@ -170,8 +172,6 @@ Global
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target wch_ch32v307|x64.Build.0 = target wch_ch32v307|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.ActiveCfg = target x86_64-w64-mingw32|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.Build.0 = target x86_64-w64-mingw32|x64
-		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_p4|x64.ActiveCfg = target xtensa_esp32_p4|x64
-		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_p4|x64.Build.0 = target xtensa_esp32_p4|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = target xtensa_esp32_s3_riscv_cop|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.Build.0 = target xtensa_esp32_s3_riscv_cop|x64
 		{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.ActiveCfg = target xtensa_esp32_s3|x64