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sh4: split xffr array. Fix FPCB_PAD on windows
Split xffr[32] into xf[16] and fr[16]. Set FPCB_PAD size to 64_KB. Issue #1736 Get rid of shil_param::reg_aofs
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9 files changed

+111
-112
lines changed

9 files changed

+111
-112
lines changed

‎core/hw/sh4/dyna/shil.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,11 +25,11 @@ u32 getRegOffset(Sh4RegType reg)
2525
}
2626
if (reg >= reg_fr_0 && reg <= reg_fr_15) {
2727
const size_t regofs = (reg - reg_fr_0) * sizeof(float);
28-
return offsetof(Sh4Context, xffr[16]) + regofs;
28+
return offsetof(Sh4Context, fr[0]) + regofs;
2929
}
3030
if (reg >= reg_xf_0 && reg <= reg_xf_15) {
3131
const size_t regofs = (reg - reg_xf_0) * sizeof(float);
32-
return offsetof(Sh4Context, xffr[0]) + regofs;
32+
return offsetof(Sh4Context, xf[0]) + regofs;
3333
}
3434
switch (reg)
3535
{

‎core/hw/sh4/dyna/shil.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,6 @@ struct shil_param
234234
u32* reg_ptr(Sh4Context& ctx) const { verify(is_reg()); return GetRegPtr(ctx, _reg); }
235235
u32 reg_offset() const { verify(is_reg()); return getRegOffset(_reg); }
236236
s32 reg_nofs() const { verify(is_reg()); return (int)getRegOffset(_reg) - sizeof(Sh4Context); }
237-
u32 reg_aofs() const { return -reg_nofs(); }
238237

239238
u32 imm_value() const { verify(is_imm()); return _imm; }
240239

‎core/hw/sh4/interpr/sh4_fpu.cpp‎

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@ sh4op(i1111_nnnn_mmmm_0000)
3434
{
3535
u32 n = GetN(op);
3636
u32 m = GetM(op);
37-
ctx->fr(n) += ctx->fr(m);
38-
CHECK_FPU_32(ctx->fr(n));
37+
ctx->fr[n] += ctx->fr[m];
38+
CHECK_FPU_32(ctx->fr[n]);
3939
}
4040
else
4141
{
@@ -53,8 +53,8 @@ sh4op(i1111_nnnn_mmmm_0001)
5353
u32 n = GetN(op);
5454
u32 m = GetM(op);
5555

56-
ctx->fr(n) -= ctx->fr(m);
57-
CHECK_FPU_32(ctx->fr(n));
56+
ctx->fr[n] -= ctx->fr[m];
57+
CHECK_FPU_32(ctx->fr[n]);
5858
}
5959
else
6060
{
@@ -70,8 +70,8 @@ sh4op(i1111_nnnn_mmmm_0010)
7070
{
7171
u32 n = GetN(op);
7272
u32 m = GetM(op);
73-
ctx->fr(n) *= ctx->fr(m);
74-
CHECK_FPU_32(ctx->fr(n));
73+
ctx->fr[n] *= ctx->fr[m];
74+
CHECK_FPU_32(ctx->fr[n]);
7575
}
7676
else
7777
{
@@ -88,9 +88,9 @@ sh4op(i1111_nnnn_mmmm_0011)
8888
u32 n = GetN(op);
8989
u32 m = GetM(op);
9090

91-
ctx->fr(n) /= ctx->fr(m);
91+
ctx->fr[n] /= ctx->fr[m];
9292

93-
CHECK_FPU_32(ctx->fr(n));
93+
CHECK_FPU_32(ctx->fr[n]);
9494
}
9595
else
9696
{
@@ -107,7 +107,7 @@ sh4op(i1111_nnnn_mmmm_0100)
107107
u32 n = GetN(op);
108108
u32 m = GetM(op);
109109

110-
ctx->sr.T = ctx->fr(m) == ctx->fr(n);
110+
ctx->sr.T = ctx->fr[m] == ctx->fr[n];
111111
}
112112
else
113113
{
@@ -122,7 +122,7 @@ sh4op(i1111_nnnn_mmmm_0101)
122122
u32 n = GetN(op);
123123
u32 m = GetM(op);
124124

125-
if (ctx->fr(n) > ctx->fr(m))
125+
if (ctx->fr[n] > ctx->fr[m])
126126
ctx->sr.T = 1;
127127
else
128128
ctx->sr.T = 0;
@@ -281,7 +281,7 @@ sh4op(i1111_nnnn_mmmm_1100)
281281
{
282282
u32 n = GetN(op);
283283
u32 m = GetM(op);
284-
ctx->fr(n) = ctx->fr(m);
284+
ctx->fr[n] = ctx->fr[m];
285285
}
286286
else
287287
{
@@ -339,14 +339,14 @@ sh4op(i1111_nnn0_1111_1101)
339339
#ifdef NATIVE_FSCA
340340
float rads = pi_index / (65536.0f / 2) * float(M_PI);
341341

342-
ctx->fr(n + 0) = sinf(rads);
343-
ctx->fr(n + 1) = cosf(rads);
342+
ctx->fr[n + 0] = sinf(rads);
343+
ctx->fr[n + 1] = cosf(rads);
344344

345-
CHECK_FPU_32(ctx->fr(n));
346-
CHECK_FPU_32(ctx->fr(n + 1));
345+
CHECK_FPU_32(ctx->fr[n]);
346+
CHECK_FPU_32(ctx->fr[n + 1]);
347347
#else
348-
ctx->fr(n + 0) = sin_table[pi_index].u[0];
349-
ctx->fr(n + 1) = sin_table[pi_index].u[1];
348+
ctx->fr[n + 0] = sin_table[pi_index].u[0];
349+
ctx->fr[n + 1] = sin_table[pi_index].u[1];
350350
#endif
351351

352352
}
@@ -360,8 +360,8 @@ sh4op(i1111_nnnn_0111_1101)
360360
u32 n = GetN(op);
361361
if (ctx->fpscr.PR==0)
362362
{
363-
ctx->fr(n) = 1.f / sqrtf(ctx->fr(n));
364-
CHECK_FPU_32(ctx->fr(n));
363+
ctx->fr[n] = 1.f / sqrtf(ctx->fr[n]);
364+
CHECK_FPU_32(ctx->fr[n]);
365365
}
366366
else
367367
iNimp("FSRRA : Double precision mode");
@@ -404,12 +404,12 @@ sh4op(i1111_nnmm_1110_1101)
404404
int m=(GetN(op)&0x3)<<2;
405405
if (ctx->fpscr.PR == 0)
406406
{
407-
double idp = (double)ctx->fr(n + 0) * ctx->fr(m + 0);
408-
idp += (double)ctx->fr(n + 1) * ctx->fr(m + 1);
409-
idp += (double)ctx->fr(n + 2) * ctx->fr(m + 2);
410-
idp += (double)ctx->fr(n + 3) * ctx->fr(m + 3);
407+
double idp = (double)ctx->fr[n + 0] * ctx->fr[m + 0];
408+
idp += (double)ctx->fr[n + 1] * ctx->fr[m + 1];
409+
idp += (double)ctx->fr[n + 2] * ctx->fr[m + 2];
410+
idp += (double)ctx->fr[n + 3] * ctx->fr[m + 3];
411411

412-
ctx->fr(n + 3) = fixNaN((float)idp);
412+
ctx->fr[n + 3] = fixNaN((float)idp);
413413
}
414414
else
415415
{
@@ -425,7 +425,7 @@ sh4op(i1111_nnnn_1000_1101)
425425

426426
u32 n = GetN(op);
427427

428-
ctx->fr(n) = 0.0f;
428+
ctx->fr[n] = 0.0f;
429429

430430
}
431431

@@ -437,7 +437,7 @@ sh4op(i1111_nnnn_1001_1101)
437437

438438
u32 n = GetN(op);
439439

440-
ctx->fr(n) = 1.0f;
440+
ctx->fr[n] = 1.0f;
441441
}
442442

443443
//flds <FREG_N>,FPUL
@@ -461,7 +461,7 @@ sh4op(i1111_nnnn_0010_1101)
461461
if (ctx->fpscr.PR == 0)
462462
{
463463
u32 n = GetN(op);
464-
ctx->fr(n) = (float)(int)ctx->fpul;
464+
ctx->fr[n] = (float)(int)ctx->fpul;
465465
}
466466
else
467467
{
@@ -503,8 +503,8 @@ sh4op(i1111_nnnn_0110_1101)
503503
{
504504
u32 n = GetN(op);
505505

506-
ctx->fr(n) = sqrtf(ctx->fr(n));
507-
CHECK_FPU_32(ctx->fr(n));
506+
ctx->fr[n] = sqrtf(ctx->fr[n]);
507+
CHECK_FPU_32(ctx->fr[n]);
508508
}
509509
else
510510
{
@@ -519,14 +519,14 @@ sh4op(i1111_nnnn_0011_1101)
519519
if (ctx->fpscr.PR == 0)
520520
{
521521
u32 n = GetN(op);
522-
ctx->fpul = (u32)(s32)ctx->fr(n);
522+
ctx->fpul = (u32)(s32)ctx->fr[n];
523523

524524
if ((s32)ctx->fpul > 0x7fffff80)
525525
ctx->fpul = 0x7fffffff;
526526
// Intel CPUs convert out of range float numbers to 0x80000000. Manually set the correct sign
527-
else if (ctx->fpul == 0x80000000 && ctx->fr(n) == ctx->fr(n))
527+
else if (ctx->fpul == 0x80000000 && ctx->fr[n] == ctx->fr[n])
528528
{
529-
if (*(int *)&ctx->fr(n) > 0) // Using integer math to avoid issues with Inf and NaN
529+
if (*(int *)&ctx->fr[n] > 0) // Using integer math to avoid issues with Inf and NaN
530530
ctx->fpul--;
531531
}
532532
}
@@ -554,8 +554,8 @@ sh4op(i1111_nnnn_mmmm_1110)
554554
u32 n = GetN(op);
555555
u32 m = GetM(op);
556556

557-
ctx->fr(n) = std::fma(ctx->fr(0), ctx->fr(m), ctx->fr(n));
558-
CHECK_FPU_32(ctx->fr(n));
557+
ctx->fr[n] = std::fma(ctx->fr[0], ctx->fr[m], ctx->fr[n]);
558+
CHECK_FPU_32(ctx->fr[n]);
559559
}
560560
else
561561
{
@@ -578,30 +578,30 @@ sh4op(i1111_nn01_1111_1101)
578578

579579
if (ctx->fpscr.PR==0)
580580
{
581-
double v1 = (double)ctx->xf(0) * ctx->fr(n + 0) +
582-
(double)ctx->xf(4) * ctx->fr(n + 1) +
583-
(double)ctx->xf(8) * ctx->fr(n + 2) +
584-
(double)ctx->xf(12) * ctx->fr(n + 3);
585-
586-
double v2 = (double)ctx->xf(1) * ctx->fr(n + 0) +
587-
(double)ctx->xf(5) * ctx->fr(n + 1) +
588-
(double)ctx->xf(9) * ctx->fr(n + 2) +
589-
(double)ctx->xf(13) * ctx->fr(n + 3);
590-
591-
double v3 = (double)ctx->xf(2) * ctx->fr(n + 0) +
592-
(double)ctx->xf(6) * ctx->fr(n + 1) +
593-
(double)ctx->xf(10) * ctx->fr(n + 2) +
594-
(double)ctx->xf(14) * ctx->fr(n + 3);
595-
596-
double v4 = (double)ctx->xf(3) * ctx->fr(n + 0) +
597-
(double)ctx->xf(7) * ctx->fr(n + 1) +
598-
(double)ctx->xf(11) * ctx->fr(n + 2) +
599-
(double)ctx->xf(15) * ctx->fr(n + 3);
600-
601-
ctx->fr(n + 0) = fixNaN((float)v1);
602-
ctx->fr(n + 1) = fixNaN((float)v2);
603-
ctx->fr(n + 2) = fixNaN((float)v3);
604-
ctx->fr(n + 3) = fixNaN((float)v4);
581+
double v1 = (double)ctx->xf[0] * ctx->fr[n + 0] +
582+
(double)ctx->xf[4] * ctx->fr[n + 1] +
583+
(double)ctx->xf[8] * ctx->fr[n + 2] +
584+
(double)ctx->xf[12] * ctx->fr[n + 3];
585+
586+
double v2 = (double)ctx->xf[1] * ctx->fr[n + 0] +
587+
(double)ctx->xf[5] * ctx->fr[n + 1] +
588+
(double)ctx->xf[9] * ctx->fr[n + 2] +
589+
(double)ctx->xf[13] * ctx->fr[n + 3];
590+
591+
double v3 = (double)ctx->xf[2] * ctx->fr[n + 0] +
592+
(double)ctx->xf[6] * ctx->fr[n + 1] +
593+
(double)ctx->xf[10] * ctx->fr[n + 2] +
594+
(double)ctx->xf[14] * ctx->fr[n + 3];
595+
596+
double v4 = (double)ctx->xf[3] * ctx->fr[n + 0] +
597+
(double)ctx->xf[7] * ctx->fr[n + 1] +
598+
(double)ctx->xf[11] * ctx->fr[n + 2] +
599+
(double)ctx->xf[15] * ctx->fr[n + 3];
600+
601+
ctx->fr[n + 0] = fixNaN((float)v1);
602+
ctx->fr[n + 1] = fixNaN((float)v2);
603+
ctx->fr[n + 2] = fixNaN((float)v3);
604+
ctx->fr[n + 3] = fixNaN((float)v4);
605605
}
606606
else
607607
{

‎core/hw/sh4/sh4_core_regs.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ void DYNACALL Sh4Context::UpdateFPSCR(Sh4Context *ctx)
133133
{
134134
if (ctx->fpscr.FR != ctx->old_fpscr.FR)
135135
// FPU bank change
136-
std::swap((f32 (&)[16])ctx->xffr, *(f32 (*)[16])&ctx->xffr[16]);
136+
std::swap(ctx->xf, ctx->fr);
137137

138138
ctx->old_fpscr = ctx->fpscr;
139139
setHostRoundingMode(ctx->fpscr.RM, ctx->fpscr.DN);

‎core/hw/sh4/sh4_if.h‎

Lines changed: 16 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ struct fpscr_t
103103
class Sh4Executor
104104
{
105105
public:
106-
virtual ~Sh4Executor() {}
106+
virtual ~Sh4Executor() = default;
107107
virtual void Run() = 0;
108108
virtual void Start() = 0;
109109
virtual void Stop() = 0;
@@ -131,7 +131,8 @@ struct alignas(64) Sh4Context
131131
{
132132
SQBuffer sq_buffer[2];
133133

134-
f32 xffr[32];
134+
float xf[16];
135+
float fr[16];
135136
u32 r[16];
136137

137138
union
@@ -170,44 +171,36 @@ struct alignas(64) Sh4Context
170171
u64 raw[64];
171172
};
172173

173-
f32& fr(int idx) {
174-
assert(idx >= 0 && idx <= 15);
175-
return xffr[idx + 16];
176-
}
177-
f32& xf(int idx) {
178-
assert(idx >= 0 && idx <= 15);
179-
return xffr[idx];
180-
}
181174
u32& fr_hex(int idx) {
182175
assert(idx >= 0 && idx <= 15);
183-
return reinterpret_cast<u32&>(fr(idx));
176+
return reinterpret_cast<u32&>(fr[idx]);
184177
}
185178
u64& dr_hex(int idx) {
186179
assert(idx >= 0 && idx <= 7);
187-
return *reinterpret_cast<u64 *>(&fr(idx * 2));
180+
return *reinterpret_cast<u64 *>(&fr[idx * 2]);
188181
}
189182
u64& xd_hex(int idx) {
190183
assert(idx >= 0 && idx <= 7);
191-
return *reinterpret_cast<u64 *>(&xf(idx * 2));
184+
return *reinterpret_cast<u64 *>(&xf[idx * 2]);
192185
}
193186

194-
f64 getDR(u32 n)
187+
double getDR(u32 n)
195188
{
196189
assert(n <= 7);
197190
DoubleReg t;
198-
t.sgl[1] = fr(n * 2);
199-
t.sgl[0] = fr(n * 2 + 1);
191+
t.sgl[1] = fr[n * 2];
192+
t.sgl[0] = fr[n * 2 + 1];
200193

201194
return t.dbl;
202195
}
203196

204-
void setDR(u32 n, f64 val)
197+
void setDR(u32 n, double val)
205198
{
206199
assert(n <= 7);
207200
DoubleReg t;
208201
t.dbl = val;
209-
fr(n * 2) = t.sgl[1];
210-
fr(n * 2 + 1) = t.sgl[0];
202+
fr[n * 2] = t.sgl[1];
203+
fr[n * 2 + 1] = t.sgl[0];
211204
}
212205

213206
static void DYNACALL UpdateFPSCR(Sh4Context *ctx);
@@ -216,8 +209,8 @@ struct alignas(64) Sh4Context
216209
private:
217210
union DoubleReg
218211
{
219-
f64 dbl;
220-
f32 sgl[2];
212+
double dbl;
213+
float sgl[2];
221214
};
222215
};
223216
static_assert(sizeof(Sh4Context) == 512, "Invalid Sh4Context size");
@@ -230,7 +223,8 @@ static_assert(sizeof(Sh4Context) == 512, "Invalid Sh4Context size");
230223
// want to be an i8r4 value that can be substracted in one op (such as 0x4100000)
231224
#define FPCB_PAD 0x100000
232225
#else
233-
#define FPCB_PAD PAGE_SIZE
226+
// For other systems we could use PAGE_SIZE, except on windows that has a 64 KB granularity for memory mapping
227+
#define FPCB_PAD 64_KB
234228
#endif
235229
struct alignas(PAGE_SIZE) Sh4RCB
236230
{

‎core/hw/sh4/sh4_opcode_list.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -461,25 +461,25 @@ std::string disassemble_op(const char* tx1, u32 pc, u16 opcode)
461461
}
462462
else if (strcmp2(tx1,"FREG_N>"))
463463
{
464-
sprintf(buf,"FR%d=%f ", GetN(opcode), p_sh4rcb->cntx.xffr[16 + GetN(opcode)]);
464+
sprintf(buf,"FR%d=%f ", GetN(opcode), p_sh4rcb->cntx.fr[GetN(opcode)]);
465465
regs += buf;
466466
sprintf(buf,"FR%d",GetN(opcode));
467467
}
468468
else if (strcmp2(tx1,"FREG_M>"))
469469
{
470-
sprintf(buf,"FR%d=%f ", GetM(opcode), p_sh4rcb->cntx.xffr[16 + GetM(opcode)]);
470+
sprintf(buf,"FR%d=%f ", GetM(opcode), p_sh4rcb->cntx.fr[GetM(opcode)]);
471471
regs += buf;
472472
sprintf(buf,"FR%d",GetM(opcode));
473473
}
474474
else if (strcmp2(tx1, "FREG_M_SD_F>"))
475475
{
476-
sprintf(buf,"FR%d=%f ", GetM(opcode), p_sh4rcb->cntx.xffr[16 + GetM(opcode)]);
476+
sprintf(buf,"FR%d=%f ", GetM(opcode), p_sh4rcb->cntx.fr[GetM(opcode)]);
477477
regs += buf;
478478
sprintf(buf,"FR%d", GetM(opcode));
479479
}
480480
else if (strcmp2(tx1,"FREG_0>"))
481481
{
482-
sprintf(buf,"FR0=%f ", p_sh4rcb->cntx.xffr[16]);
482+
sprintf(buf,"FR0=%f ", p_sh4rcb->cntx.fr[0]);
483483
regs += buf;
484484
sprintf(buf,"FR0");
485485
}

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