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Releases: ggml-org/llama.cpp

b9084

09 May 03:27
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b9084

hexagon: add HTP kernel for GGML_OP_GATED_DELTA_NET (#22837)

Implement the Gated Delta Net recurrence on HVX with:

  • 4-row fused kernels for PP (prompt processing) path
  • 8-row fused kernels for TG (token generation) path, reducing
    K/Q/gate vector reload overhead by 2x
  • Separate PP/TG thread functions for I-cache isolation
  • VTCM state scratchpad with DMA in/out for TG single-cycle access
  • Vectorized gate exp via hvx_exp_f32

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b9082

08 May 22:21
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b9082

Feature hexagon l2 norm (#22816)

  • L2_NORM Updates

  • Addressed PR Comments

  • ggml-hexagon: add L2_NORM HVX kernel for Hexagon backend

  • hex-unary: remove supported_unary_nc since the outer loop is the same for all unary ops

Co-authored-by: Max Krasnyansky maxk@qti.qualcomm.com

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b9081

08 May 22:18
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b9081

common : do not wrap raw strings in schema parser for tagged parsers (#22827)

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b9080

08 May 21:05
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b9080

model : support Gemma4_26B_A4B_NVFP4 (#22804)

  • Gemma4_26B_A4B_NvFp4 hf checkpoint convert to gguf format fixes

Signed-off-by: ynankani ynankani@nvidia.com

  • Apply suggestions from code review

Co-authored-by: Sigbjørn Skjæret sigbjorn.skjaeret@scala.com

  • Address review comments

Signed-off-by: ynankani ynankani@nvidia.com

  • fix CRLF

Signed-off-by: ynankani ynankani@nvidia.com

  • Lint error fix

Signed-off-by: ynankani ynankani@nvidia.com

Signed-off-by: ynankani ynankani@nvidia.com
Co-authored-by: Sigbjørn Skjæret sigbjorn.skjaeret@scala.com

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b9079

08 May 20:23
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b9079
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b9079

common : revert reasoning budget +inf logit bias (#22740)

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b9077

08 May 19:29
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b9077
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b9077

server: support Vertex AI compatible API (#22545)

  • server: support Vertex AI compatible API

  • a bit safer

  • support other AIP_* env var

  • various fixes

  • if AIP_MODE is unset, do nothing

  • fix test case

  • fix windows build

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b9076

08 May 18:53
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b9076

server: (router) expose child model info from router's /v1/models (#22683)

  • server: (router) expose child model info from router's /v1/models

  • update docs

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b9075

08 May 17:37
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b9075
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b9075

cuda: fuse snake activation (mul, sin, sqr, mul, add) (#22667)

  • cuda: fuse snake activation (mul, sin, sqr, mul, add)

Add ggml_cuda_op_snake_fused with F32 / F16 / BF16 templates. The
matcher recognizes the naive 5 op decomposition emitted by audio
decoders (BigVGAN, Vocos) for snake activation
y = x + sin(a*x)^2 * inv_b and rewrites it to a single elementwise
kernel.

Add test_snake_fuse comparing CPU naive vs CUDA fused across
F32 / F16 / BF16.

  • cuda: address review feedback from @am17an

Use ggml_cuda_cast for F32/F16/BF16 conversions and rename
kernel_snake to snake_kernel to match upstream conventions.

  • cuda: snake fusion fastdiv on T_len, Suggested-by: @am17an

  • Update tests/test-backend-ops.cpp

Co-authored-by: Aman Gupta amangupta052@gmail.com

  • cuda: snake fusion check add->type matches x->type

Address review feedback from @am17an

  • cuda: snake fusion check add->type matches x->type

Moved for readability (equivalent)
Address review feedback from @am17an

Co-authored-by: Aman Gupta amangupta052@gmail.com

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b9073

08 May 16:04
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CUDA: lower-case PCI bus id, standardize for ggml (#22820)

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b9072

08 May 13:26
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b9072
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b9072

vulkan: fix spv shadowing (#22760)

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