Skip to content

Commit 13e920d

Browse files
Haijun Liudavem330
Haijun Liu
authored and
davem330
committed
net: wwan: t7xx: Add core components
Registers the t7xx device driver with the kernel. Setup all the core components: PCIe layer, Modem Host Cross Core Interface (MHCCIF), modem control operations, modem state machine, and build infrastructure. * PCIe layer code implements driver probe and removal. * MHCCIF provides interrupt channels to communicate events such as handshake, PM and port enumeration. * Modem control implements the entry point for modem init, reset and exit. * The modem status monitor is a state machine used by modem control to complete initialization and stop. It is used also to propagate exception events reported by other components. Signed-off-by: Haijun Liu <[email protected]> Signed-off-by: Chandrashekar Devegowda <[email protected]> Co-developed-by: Ricardo Martinez <[email protected]> Signed-off-by: Ricardo Martinez <[email protected]> Reviewed-by: Loic Poulain <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergey Ryazanov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
1 parent 39d4390 commit 13e920d

File tree

14 files changed

+2108
-0
lines changed

14 files changed

+2108
-0
lines changed

‎drivers/net/wwan/Kconfig‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,20 @@ config IOSM
105105

106106
If unsure, say N.
107107

108+
config MTK_T7XX
109+
tristate "MediaTek PCIe 5G WWAN modem T7xx device"
110+
depends on PCI
111+
help
112+
Enables MediaTek PCIe based 5G WWAN modem (T7xx series) device.
113+
Adapts WWAN framework and provides network interface like wwan0
114+
and tty interfaces like wwan0at0 (AT protocol), wwan0mbim0
115+
(MBIM protocol), etc.
116+
117+
To compile this driver as a module, choose M here: the module will be
118+
called mtk_t7xx.
119+
120+
If unsure, say N.
121+
108122
endif # WWAN
109123

110124
endmenu

‎drivers/net/wwan/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,4 @@ obj-$(CONFIG_MHI_WWAN_MBIM) += mhi_wwan_mbim.o
1313
obj-$(CONFIG_QCOM_BAM_DMUX) += qcom_bam_dmux.o
1414
obj-$(CONFIG_RPMSG_WWAN_CTRL) += rpmsg_wwan_ctrl.o
1515
obj-$(CONFIG_IOSM) += iosm/
16+
obj-$(CONFIG_MTK_T7XX) += t7xx/

‎drivers/net/wwan/t7xx/Makefile‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
# SPDX-License-Identifier: GPL-2.0-only
2+
3+
ccflags-y += -Werror
4+
5+
obj-${CONFIG_MTK_T7XX} := mtk_t7xx.o
6+
mtk_t7xx-y:= t7xx_pci.o \
7+
t7xx_pcie_mac.o \
8+
t7xx_mhccif.o \
9+
t7xx_state_monitor.o \
10+
t7xx_modem_ops.o \
11+
t7xx_cldma.o \
12+
t7xx_hif_cldma.o \

‎drivers/net/wwan/t7xx/t7xx_mhccif.c‎

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (c) 2021, MediaTek Inc.
4+
* Copyright (c) 2021-2022, Intel Corporation.
5+
*
6+
* Authors:
7+
* Haijun Liu <[email protected]>
8+
* Sreehari Kancharla <[email protected]>
9+
*
10+
* Contributors:
11+
* Amir Hanania <[email protected]>
12+
* Ricardo Martinez <[email protected]>
13+
*/
14+
15+
#include <linux/bits.h>
16+
#include <linux/completion.h>
17+
#include <linux/dev_printk.h>
18+
#include <linux/io.h>
19+
#include <linux/irqreturn.h>
20+
21+
#include "t7xx_mhccif.h"
22+
#include "t7xx_modem_ops.h"
23+
#include "t7xx_pci.h"
24+
#include "t7xx_pcie_mac.h"
25+
#include "t7xx_reg.h"
26+
27+
static void t7xx_mhccif_clear_interrupts(struct t7xx_pci_dev *t7xx_dev, u32 mask)
28+
{
29+
void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
30+
31+
/* Clear level 2 interrupt */
32+
iowrite32(mask, mhccif_pbase + REG_EP2RC_SW_INT_ACK);
33+
/* Ensure write is complete */
34+
t7xx_mhccif_read_sw_int_sts(t7xx_dev);
35+
/* Clear level 1 interrupt */
36+
t7xx_pcie_mac_clear_int_status(t7xx_dev, MHCCIF_INT);
37+
}
38+
39+
static irqreturn_t t7xx_mhccif_isr_thread(int irq, void *data)
40+
{
41+
struct t7xx_pci_dev *t7xx_dev = data;
42+
u32 int_status, val;
43+
44+
val = T7XX_L1_1_BIT(1) | T7XX_L1_2_BIT(1);
45+
iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);
46+
47+
int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);
48+
if (int_status & D2H_SW_INT_MASK) {
49+
int ret = t7xx_pci_mhccif_isr(t7xx_dev);
50+
51+
if (ret)
52+
dev_err(&t7xx_dev->pdev->dev, "PCI MHCCIF ISR failure: %d", ret);
53+
}
54+
55+
t7xx_mhccif_clear_interrupts(t7xx_dev, int_status);
56+
t7xx_pcie_mac_set_int(t7xx_dev, MHCCIF_INT);
57+
return IRQ_HANDLED;
58+
}
59+
60+
u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev)
61+
{
62+
return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_STS);
63+
}
64+
65+
void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val)
66+
{
67+
iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET);
68+
}
69+
70+
void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val)
71+
{
72+
iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR);
73+
}
74+
75+
u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev)
76+
{
77+
return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK);
78+
}
79+
80+
static irqreturn_t t7xx_mhccif_isr_handler(int irq, void *data)
81+
{
82+
return IRQ_WAKE_THREAD;
83+
}
84+
85+
void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev)
86+
{
87+
t7xx_dev->base_addr.mhccif_rc_base = t7xx_dev->base_addr.pcie_ext_reg_base +
88+
MHCCIF_RC_DEV_BASE -
89+
t7xx_dev->base_addr.pcie_dev_reg_trsl_addr;
90+
91+
t7xx_dev->intr_handler[MHCCIF_INT] = t7xx_mhccif_isr_handler;
92+
t7xx_dev->intr_thread[MHCCIF_INT] = t7xx_mhccif_isr_thread;
93+
t7xx_dev->callback_param[MHCCIF_INT] = t7xx_dev;
94+
}
95+
96+
void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel)
97+
{
98+
void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
99+
100+
iowrite32(BIT(channel), mhccif_pbase + REG_RC2EP_SW_BSY);
101+
iowrite32(channel, mhccif_pbase + REG_RC2EP_SW_TCHNUM);
102+
}

‎drivers/net/wwan/t7xx/t7xx_mhccif.h‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only
2+
*
3+
* Copyright (c) 2021, MediaTek Inc.
4+
* Copyright (c) 2021-2022, Intel Corporation.
5+
*
6+
* Authors:
7+
* Haijun Liu <[email protected]>
8+
* Sreehari Kancharla <[email protected]>
9+
*
10+
* Contributors:
11+
* Amir Hanania <[email protected]>
12+
* Ricardo Martinez <[email protected]>
13+
*/
14+
15+
#ifndef __T7XX_MHCCIF_H__
16+
#define __T7XX_MHCCIF_H__
17+
18+
#include <linux/types.h>
19+
20+
#include "t7xx_pci.h"
21+
#include "t7xx_reg.h"
22+
23+
#define D2H_SW_INT_MASK (D2H_INT_EXCEPTION_INIT | \
24+
D2H_INT_EXCEPTION_INIT_DONE | \
25+
D2H_INT_EXCEPTION_CLEARQ_DONE | \
26+
D2H_INT_EXCEPTION_ALLQ_RESET | \
27+
D2H_INT_PORT_ENUM | \
28+
D2H_INT_ASYNC_MD_HK)
29+
30+
void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val);
31+
void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val);
32+
u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev);
33+
void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev);
34+
u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev);
35+
void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel);
36+
37+
#endif /*__T7XX_MHCCIF_H__ */

0 commit comments

Comments
 (0)