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add test for simd from array repeat codegen
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//@ add-minicore
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//@ revisions: X86 AARCH64 RISCV
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//@ [X86] compile-flags: -Copt-level=3 --target=x86_64-unknown-linux-gnu
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//@ [X86] needs-llvm-components: x86
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//@ [AARCH64] compile-flags: -Copt-level=3 --target=aarch64-unknown-linux-gnu
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//@ [AARCH64] needs-llvm-components: aarch64
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//@ [RISCV] compile-flags: --target riscv64gc-unknown-none-elf
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//@ [RISCV] needs-llvm-components: riscv
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#![crate_type = "lib"]
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#![feature(repr_simd)]
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#![feature(no_core)]
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#![no_std]
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#![no_core]
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extern crate minicore;
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use minicore::*;
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#[repr(simd)]
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pub struct Simd<T, const N: usize>(pub [T; N]);
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pub type u8x16 = Simd<u8, 16>;
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// Regression test for https://github.com/rust-lang/rust/issues/97804.
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#[unsafe(no_mangle)]
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fn foo(v: u16, p: &mut [u8; 16]) {
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// An array repeat transmuted into a SIMD type should emit a canonical LLVM splat sequence:
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//
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// CHECK-LABEL: foo
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// CHECK: start
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// CHECK-NEXT: %0 = insertelement <8 x i16> poison, i16 %v, i64 0
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// CHECK-NEXT: %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> zeroinitializer
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// CHECK-NEXT: store <8 x i16> %1, ptr %p, align 1
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// CHECK-NEXT: ret void
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unsafe {
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let v: u8x16 = mem::transmute([v; 8]);
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*p = mem::transmute(v);
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}
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}

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