USB3_to_DA/FPGA_nativelink_simulation.rpt at master · zwc12/USB3_to_DA · GitHub

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Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cycloneiii
Quartus root          :  d:/apps/altera/13.1/quartus/bin64/
Quartus sim root      :  d:/apps/altera/13.1/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :
Sim SDF file          :
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script d:/apps/altera/13.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File FPGA_run_msim_rtl_verilog.do already exists - backing up current file as FPGA_run_msim_rtl_verilog.do.bak6
Info: Spawning ModelSim-Altera Simulation software