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Modelsim is exhibiting weird filepath behavior. See the following mpf, from a user running windows:
Project_File_0 = C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissionslab3Oscar Alvarezmodelsim/UsersIrn19Desktop�utograderDD_Grader-mainlab-testbencheslab3�dder_true_testbench.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_1 = C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissions/lab3/Oscar Alvarez/36284998/P4/cla4.vhd
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1677213661 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_2 = C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissions/lab3/Oscar Alvarez/36284998/P2/cla2.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1677213661 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_3 = C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissions/lab3/Oscar Alvarez/36284998/P1/fa.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1677213661 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_4 = C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissions/lab3/Oscar Alvarez/36284998/P5, P6, P7/adder.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1677213661 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_5 = C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissions/lab3/Oscar Alvarez/36284998/P3/cgen2.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1677213661 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
The accompyaning error when running the grader:
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
Start time: 23:41:10 on Feb 23,2023
vcom -work work -2002 -explicit C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissionslab3Oscar Alvarezmodelsim/UsersIrn19Desktop�utograderDD_Grader-mainlab-testbencheslab3�dder_true_testbench.vhd
** Error: (vcom-7) Failed to open design unit file "C:/Users/Irn19/Desktop/autograder/DD_Grader-main/Submissionslab3Oscar Alvarezmodelsim/UsersIrn19Desktop�utograderDD_Grader-mainlab-testbencheslab3�dder_true_testbench.vhd" in read mode.
No such file or directory. (errno = ENOENT)
End time: 23:41:10 on Feb 23,2023, Elapsed time: 0:00:00
Errors: 1, Warnings: 0
Notice the non-ascii letters. These paths don't actuallly exist. That's definitely not supposed to happen.
I cannot reproduce these bugs, but I am on Linux. I'll download a windows VM and see if that does the trick.
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