Ryzen 9000 Core Frequency Bugfix#1548
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Zen5 (Ryzen 9000) has a changed register mapping for readout core frequency
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libre-hardware-monitor.zip Update: |
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Tested with 9950x and it occasionally shows similar values, but most of the time, the values differ from HWInfo.
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I think this is an effect of reading out the cores. Hwinfo will form mean values when reading. |
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The update frequency for both is set to 250ms. 2024-12-04.00.11.57.mp4 |
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👍 Thank you! This is working perfectly |
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Hello, Great work, and thank you! |
* fixed Package Power and Core power Calculation, use ESU for power scaling * Changed DateTime.Now to UtcNow (better performance) * Added Effective core clock * Added Average Core clock and Average effective clock
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Update |
Core effective clock is now calculated in Amd17Cpu/Core
Ratio > 1 is not possible
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Latest patch works as expected with 9800X3D for me. |
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Nice work @sebastian-dev 🎉 |
* Ryzen 9000 Core Frequency Bugfix Zen5 (Ryzen 9000) has a changed register mapping for readout core frequency * Update Ryzen 9000 and Core Clock * fixed Package Power and Core power Calculation, use ESU for power scaling * Changed DateTime.Now to UtcNow (better performance) * Added Effective core clock * Added Average Core clock and Average effective clock * Remove Effective clock from SMU Core effective clock is now calculated in Amd17Cpu/Core * Fix Clock Ratio calculation. Ratio > 1 is not possible * Update Amd17Cpu.cs --------- Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
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hi i see this has been merged already i recently build in a 9950X3D CPU in my system and downloaded latest LibreHWMonitor here |
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Zen5 (Ryzen 9000) has a changed register mapping for readout core frequency