Property errors not detailed in LVS report

[d-m-bailey]

The output of netgen 1.5.316 reports property errors, but there are no details.

Resolving symmetries by property value.
Resolving symmetries by pin name.
Resolving symmetries by net name.
Netlists match with 26 symmetries with property errors.

Subcircuit pins:
Circuit 1: sky130_ef_io__gpiov2_pad                           |Circuit 2: sky130_ef_io__gpiov2_pad                           
--------------------------------------------------------------|--------------------------------------------------------------
PAD                                                           |PAD                                                           
VCCD                                                          |VCCD                                                          
VDDIO_Q                                                       |VDDIO_Q                                                       
VSSIO                                                         |VSSIO                                                         
VSSD                                                          |VSSD                                                          
VSSA                                                          |VSSA                                                          
VDDIO                                                         |VDDIO                                                         
VSWITCH                                                       |VSWITCH                                                       
VCCHIB                                                        |VCCHIB                                                        
VDDA                                                          |VDDA                                                          
ENABLE_H                                                      |ENABLE_H                                                      
PAD_A_ESD_0_H                                                 |PAD_A_ESD_0_H                                                 
PAD_A_ESD_1_H                                                 |PAD_A_ESD_1_H                                                 
AMUXBUS_A                                                     |AMUXBUS_A                                                     
AMUXBUS_B                                                     |AMUXBUS_B                                                     
ENABLE_VDDA_H                                                 |ENABLE_VDDA_H                                                 
ENABLE_VSWITCH_H                                              |ENABLE_VSWITCH_H                                              
TIE_LO_ESD                                                    |TIE_LO_ESD                                                    
ANALOG_POL                                                    |ANALOG_POL                                                    
ANALOG_SEL                                                    |ANALOG_SEL                                                    
HLD_H_N                                                       |HLD_H_N                                                       
IN                                                            |IN                                                            
IN_H                                                          |IN_H                                                          
OE_N                                                          |OE_N                                                          
PAD_A_NOESD_H                                                 |PAD_A_NOESD_H                                                 
HLD_OVR                                                       |HLD_OVR                                                       
DM[1]                                                         |DM[1]                                                         
DM[2]                                                         |DM[2]                                                         
DM[0]                                                         |DM[0]                                                         
SLOW                                                          |SLOW                                                          
IB_MODE_SEL                                                   |IB_MODE_SEL                                                   
VTRIP_SEL                                                     |VTRIP_SEL                                                     
INP_DIS                                                       |INP_DIS                                                       
ANALOG_EN                                                     |ANALOG_EN                                                     
ENABLE_INP_H                                                  |ENABLE_INP_H                                                  
ENABLE_VDDIO                                                  |ENABLE_VDDIO                                                  
OUT                                                           |OUT                                                           
TIE_HI_ESD                                                    |TIE_HI_ESD                                                    
VSSIO_Q                                                       |VSSIO_Q                                                       
-----------------------------------------------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_ef_io__gpiov2_pad and sky130_ef_io__gpiov2_pad are equivalent.

Final result: Circuits match uniquely.
Property errors were found.

The following cells had property errors:
 sky130_ef_io__gpiov2_pad

sky130_gpiov2_test.tgz

To reproduce

tar xzf sky130_gpiov2_test.tgz
cd sky130_gpiov2_test
./run_pad_lvs_1.sh

The LVS report is pad_1_comp.out.

The layout was extracted with magic 8.3.590 and the sky130_ef_io__gpiov2_pad.8_3_590.spice file is included in the tar file as reference.

The LVS script is using a modified sky130_fd_io.spice file that includes the following dummy resistors in sky130_fd_io__res250only_small

Rli0 PAD PAD sky130_fd_pr__res_generic_l1 W=0.23 L=0.005 m=1
Rli1 ROUT ROUT sky130_fd_pr__res_generic_l1 W=0.23 L=0.005 m=1
Rm0 PAD PAD sky130_fd_pr__res_generic_m1 W=2 L=10.07 m=1
Rm1 ROUT ROUT sky130_fd_pr__res_generic_m1 W=2 L=10.07 m=1

The size of the dummy resistors does not match the layout.

The resistor recognition layer is on a different hierarchy and so they are only extracted if the sky130_fd_io__res250only_small cell is flattened. Conversely, magic (but probably not other tools) ignores these devices if sky130_fd_io__res250only_small is not flattened.

[RTimothyEdwards]

I will investigate this to figure out why the property error doesn't get output.
However, otherwise I am inclined to just fix this in the upstream layout by either moving the resistor recognition layer into the cell with the metal, or removing the resistor recognition layer altogether. The resistors have no actual function but appear to have been intended as a kind of alignment marker that forces an LVS error if the two overlapping cells are not aligned correctly, since their separation affects the ESD characteristics of the I/O cell.

[d-m-bailey]

@RTimothyEdwards Thanks for looking into this.

Andy said that it had something to do with ESD, but I also do not see a purpose to the resistors.

Just to be clear, these are not the overlapping donut resistors that I think you are referring to. Those are in the neighboring sky130_fd_io__signal_5_sym_hv_local_5term cell and as shown in the screenshot, they do not physically overlap. There are 2 in each cell and one from each cell is on the same merged metal1. If I remember correctly, netgen merges the floating nets of devices that have a common connection, so I don't know how meaningful it is.

[RTimothyEdwards]

Oh, okay. I thought you were talking about the donut resistors (which do overlap in some cells, but not all of them).
I don't see much value in the cut resistors, but I would opt for just moving the marker layer into the same cell as the local interconnect and metal1, and then it will no longer be necessary to make a custom netlist for it.

But meanwhile, the question is why was no property printed even though there was an obvious and apparently run-of-the-mill length error. Note that the tolerance for metal resistor matching is set to 10, which is huge; basically it allows any metal resistor to match no matter what the difference is in length or width. So I think the error is that it should not have reported a property error at all. If you tighten up the tolerance value, you should see the error printed. The tolerance is set high on the principle that the metal resistor is just a net breaker, and nobody cares what the value is.