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Timing Issues with Large-Scale AXIS Crossbar (24+ Ports) – Seeking Optimization

Status: Open.

#40 In alexforencich/verilog-axis;

· Unicorn619 opened on May 29, 2025

Why used defaults state in reg defeninions

Status: Open.

#39 In alexforencich/verilog-axis;

· pavel-shushunov opened on Mar 21, 2025

RTL Linting with Verilator -Wall

Status: Open.

#38 In alexforencich/verilog-axis;

· chili-chips-ba opened on Feb 26, 2025

Implementing buffer with axis_fifo or axis_pipeline_fifo

Status: Open.

#37 In alexforencich/verilog-axis;

· keegandent opened on Oct 16, 2024

temporary store function in arb_axis_mux and axis_mux

Status: Open.

#36 In alexforencich/verilog-axis;

· Unicorn619 opened on Sep 22, 2024

axis_ll_bridge.v has some problems

Status: Open.

#35 In alexforencich/verilog-axis;

· deleteTh opened on Sep 21, 2024

Issue with tuser in axis_adapter

Status: Open.

#31 In alexforencich/verilog-axis;

· immbelgique opened on Mar 14, 2024

axis_frame_length_adjust_fifo incorrect works with small header fifo length

Status: Open.

#30 In alexforencich/verilog-axis;

· derfe4 opened on Jan 19, 2024

arbiter module renaming

Status: Open.

#20 In alexforencich/verilog-axis;

· olofk opened on Oct 12, 2022

AXIS Mux Missing first tvalid?

Status: Open.

#19 In alexforencich/verilog-axis;

· polyee13 opened on Sep 22, 2022

Questions about Clock Domain Crossing in axis_async_fifo

Status: Open.

#22 In alexforencich/verilog-axis;

· Yuan-Mao opened on Aug 24, 2022

axis_async_fifo write pointer CDC

Status: Open.

#18 In alexforencich/verilog-axis;

· Basseuph opened on Jun 12, 2022