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Add new cpuid identification (Siena, Emerald Lake) (New) #950

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Merged
kissiel merged 4 commits into from
Jan 18, 2024
Merged

Add new cpuid identification (Siena, Emerald Lake) (New) #950

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b8e1317
move one of the Bergamo's cpuids to Siena
kissiel Jan 18, 2024
3bd26e2
use proper name for Raprtor Lake and place it in the right spot
kissiel Jan 18, 2024
b1cffe3
remove dead code
kissiel Jan 18, 2024
c15ad34
add tests
kissiel Jan 18, 2024
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6 changes: 4 additions & 2 deletions providers/base/bin/cpuid.py
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Original file line number Diff line number Diff line change
Expand Up @@ -175,14 +175,16 @@ def cpuid_to_human_friendly(cpuid: str) -> str:
"AMD Milan-X": ['0xa00f12'],
"AMD ROME": ['0x830f10'],
"AMD Ryzen": ['0x810f81'],
"AMD Bergamo": ['0xaa0f01', '0xaa0f02'],
"AMD Bergamo": ['0xaa0f01'],
"AMD Siena SP6": ['0xaa0f02'],
"Broadwell": ['0x4067', '0x306d4', '0x5066', '0x406f'],
"Canon Lake": ['0x6066'],
"Cascade Lake": ['0x50655', '0x50656', '0x50657'],
"Coffee Lake": [
'0x806ea', '0x906ea', '0x906eb', '0x906ec', '0x906ed'],
"Comet Lake": ['0x806ec', '0xa065'],
"Cooper Lake": ['0x5065a', '0x5065b'],
"Emerald Rapids": ['0xc06f2'],
"Haswell": ['0x306c', '0x4065', '0x4066', '0x306f'],
"Hygon Dhyana Plus": ["0x900f22"],
"Ice Lake": ['0x606e6', '0x606a6', '0x706e6', '0x606c1'],
Expand All @@ -193,13 +195,13 @@ def cpuid_to_human_friendly(cpuid: str) -> str:
"Nehalem": ['0x106a', '0x106e5', '0x206e'],
"Pineview": ['0x106ca'],
"Penryn": ['0x1067a'],
"Raptor Lake": ['0xb0671', '0xb06f2', '0xb06f5', '0xb06a2'],
"Rocket Lake": ['0xa0671'],
"Sandy Bridge": ['0x206a', '0x206d6', '0x206d7'],
"Sapphire Rapids": ['0x806f3', '0x806f6', '0x806f7', '0x806f8'],
"Skylake": ['0x406e3', '0x506e3', '0x50654', '0x50652'],
"Tiger Lake": ['0x806c1'],
"Aderlake": ['0x906a4', '0x906A3', '0x90675', '0x90672'],
"Raptorlake": ['0xB0671', '0xB06F2', '0xB06F5', '0xB06A2'],
"Westmere": ['0x2065', '0x206c', '0x206f'],
"Whisky Lake": ['0x806eb', '0x806ec'],
}
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49 changes: 46 additions & 3 deletions providers/base/tests/test_cpuid.py
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Expand Up @@ -34,7 +34,6 @@ class CpuidMainTests(unittest.TestCase):
@patch("subprocess.check_output")
@patch("cpuid.CPUID")
def test_hygon_dhyana_plus(self, cpuid_mock, co_mock, print_mock):
#import pdb; pdb.set_trace()
call_mock = MagicMock()
call_mock.return_value = [0x900f22, 0x0, 0x0, 0x0]
cpuid_mock.return_value = call_mock
Expand All @@ -48,10 +47,54 @@ def test_hygon_dhyana_plus(self, cpuid_mock, co_mock, print_mock):
@patch("subprocess.check_output")
@patch("cpuid.CPUID")
def test_unknown_cpu(self, cpuid_mock, co_mock):
#import pdb; pdb.set_trace()
call_mock = MagicMock()
call_mock.return_value = [0xdeadbeef, 0x0, 0x0, 0x0]
cpuid_mock.return_value = call_mock
co_mock.return_value = ""
with self.assertRaises(SystemExit):
main()
main()

@patch("builtins.print")
@patch("subprocess.check_output")
@patch("cpuid.CPUID")
def test_raptor_lake(self, cpuid_mock, co_mock, print_mock):
call_mock = MagicMock()
call_mock.return_value = [0xb0671, 0x0, 0x0, 0x0]
cpuid_mock.return_value = call_mock
co_mock.return_value = ""
main()
expected_msg = "CPUID: {} which appears to be a {} processor".format(
"0xb0671", "Raptor Lake"
)
print_mock.assert_called_with(expected_msg)


@patch("builtins.print")
@patch("subprocess.check_output")
@patch("cpuid.CPUID")
def test_emerald_rapids(self, cpuid_mock, co_mock, print_mock):
call_mock = MagicMock()
call_mock.return_value = [0xc06f2, 0x0, 0x0, 0x0]
cpuid_mock.return_value = call_mock
co_mock.return_value = ""
main()
expected_msg = "CPUID: {} which appears to be a {} processor".format(
"0xc06f2", "Emerald Rapids"
)
print_mock.assert_called_with(expected_msg)


@patch("builtins.print")
@patch("subprocess.check_output")
@patch("cpuid.CPUID")
def test_amd_siena_sp6(self, cpuid_mock, co_mock, print_mock):
#import pdb; pdb.set_trace()
call_mock = MagicMock()
call_mock.return_value = [0xaa0f02, 0x0, 0x0, 0x0]
cpuid_mock.return_value = call_mock
co_mock.return_value = ""
main()
expected_msg = "CPUID: {} which appears to be a {} processor".format(
"0xaa0f02", "AMD Siena SP6"
)
print_mock.assert_called_with(expected_msg)