Fix the unwind opcode for new APX registers#112799
Conversation
|
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
|
This might also fix #112286 |
|
And #112755 😄 |
|
Any idea why this didn't show up as 0-size diffs in the original PR? We should be diffing unwind codes in SPMI. Edit: It looks like we don't: runtime/src/coreclr/tools/superpmi/superpmi/neardiffer.cpp Lines 1349 to 1381 in 57ed254 |
|
/azp run runtime-coreclr libraries-jitstress2-jitstressregs, runtime-coreclr r2r-extra |
|
Azure Pipelines successfully started running 2 pipeline(s). |
|
It seems there are few failures that needs investigation but are unrelated to the change from this PR. I will investigate to make sure and open GH issues, if needed. But this should be ready for review. r2rextra failures: https://dev.azure.com/dnceng-public/public/_build/results?buildId=959524&view=ms.vss-test-web.build-test-results-tab&runId=25542994&resultId=123196&paneView=debug |
|
@dotnet/jit-contrib |
| code->UnwindOp = (genIsValidFloatReg(reg)) ? UWOP_SAVE_XMM128_FAR : UWOP_SAVE_NONVOL_FAR; | ||
| } | ||
| code->OpInfo = (BYTE)reg; | ||
| code->OpInfo = (BYTE)(genIsValidFloatReg(reg) ? reg - XMMBASE : reg); |
There was a problem hiding this comment.
Can we add an assert that genIsValidIntReg(reg) for the else case, to help catch any future bugs or expansions in this space?
There was a problem hiding this comment.
We could even assert on the actual range of the computed value, since the unwind codes are well-defined and if they change, we want the assert to hit.
There was a problem hiding this comment.
let me do it as a follow up PR and merge this as is to unblock weekend runs.
|
/ba-g osx/arm64 seems to be timeout errors. |
APX added 8 new GPR registers and that shifted the base of floating point registers. However the shift was not getting accounted for properly while embedding the unwind code.
Also, while I was there, I realized that we didn't add the mapping of new registers for DWARF CFI unwind.
Fixes: