AArch64: Use storepair more when storing out constant values#9676
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AArch64: Use storepair more when storing out constant values#9676david-arm wants to merge 2 commits intofacebook:masterfrom
david-arm wants to merge 2 commits intofacebook:masterfrom
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ottoni
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looks good, except for small coding style nit below
| @@ -166,11 +166,19 @@ int is_adjacent_vptr64(const Vptr64& a, const Vptr64& b, int32_t step, int32_t m | |||
| return 0; | |||
| } | |||
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| bool is_valid_reg_for_storepair(Env& env, Vreg s) { | |||
| if (s.isGP()) | |||
| return true; | |||
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nit: move the return true; to previous line or wrap it in { } per coding style
We sometimes see sequences like this: store %123(...b), [addr + 8] store %124(...q), [addr] The existing storepair simplify code requires that the stored registers be physical GP registers, presumably because the lowering for storepair/storepairl cannot handle FP/SIMD regs. However, during register allocation we materialise these constants and end up with the sequence: ldimmb ... => x0 store x0, [addr + 8] ldimmq ... => x0 store x0, [addr] which then makes it very difficult to combine these into storepairs in the post-regalloc simplify pass. This PR permits combining pairs of stores prior to regalloc, provided we can show they are either: 1. A GP physical register, or 2. An integer constant that will be materialised into a GP reg.
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We sometimes see sequences like this:
store %123(...b), [addr + 8]
store %124(...q), [addr]
The existing storepair simplify code requires that the stored registers be physical GP registers, presumably because the lowering for storepair/storepairl cannot handle FP/SIMD regs. However, during register allocation we materialise these constants and end up with the sequence:
ldimmb ... => x0
store x0, [addr + 8]
ldimmq ... => x0
store x0, [addr]
which then makes it very difficult to combine these into storepairs in the post-regalloc simplify pass. This PR permits combining pairs of stores prior to regalloc, provided we can show they are either: