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@againull againull commented Dec 12, 2025

See #16929 for details.
Removed the following extensions:
sycl_ext_intel_data_flow_pipes_properties
sycl_ext_intel_dataflow_pipes
sycl_ext_intel_fpga_datapath
sycl_ext_intel_fpga_device_selector
sycl_ext_intel_fpga_kernel_arg_properties
sycl_ext_intel_fpga_kernel_interface_properties
sycl_ext_intel_fpga_lsu
sycl_ext_intel_fpga_mem
sycl_ext_intel_fpga_reg
sycl_ext_intel_fpga_task_sequence
sycl_ext_intel_mem_channel_property
sycl_ext_oneapi_annotated_arg
Moved all documentation to removed folder because all listed extensions were implemented in the code, even though some of the extensions documentation remained in proposed folder.

Removed init_mode and implement_in_csr from sycl_ext_oneapi_device_global.

@againull againull force-pushed the remove_fpga_features branch from 4ee0563 to 876871d Compare December 15, 2025 20:46
@againull againull marked this pull request as ready for review December 15, 2025 21:20
@againull againull requested review from a team as code owners December 15, 2025 21:20
| `ONEAPI_DEVICE_SELECTOR` | [See below.](#oneapi_device_selector) | This device selection environment variable can be used to limit the choice of devices available when the SYCL-using application is run. Useful for limiting devices to a certain type (like GPUs or CPUs) or backends (like Level Zero or OpenCL). This device selection mechanism is replacing `SYCL_DEVICE_FILTER` . The `ONEAPI_DEVICE_SELECTOR` syntax is shared with OpenMP and also allows sub-devices to be chosen. [See below.](#oneapi_device_selector) for a full description. |
| `ONEAPI_PVC_SEND_WAR_WA` | '1' or '0' | Controls the workaround for Erratum "FP64 register ordering violation" on Intel Ponte Vecchio GPUs. Setting `ONEAPI_PVC_SEND_WAR_WA=0` disables the workaround and is only safe if the secondary FP64 pipeline is disabled. Default is enabled ('1') and applied throughout the oneAPI software stack - including OneDNN, OneMKL, OpenCL and Level Zero Runtimes, and Intel Graphics Compiler. |
| `SYCL_DEVICE_ALLOWLIST` | See [below](#sycl_device_allowlist) | Filter out devices that do not match the pattern specified. `BackendName` accepts `host`, `opencl`, `level_zero`, `native_cpu` or `cuda`. `DeviceType` accepts `host`, `cpu`, `gpu`, `fpga`, or `acc`. `fpga` and `acc` are handled in the same manner. `DeviceVendorId` accepts uint32_t in hex form (`0xXYZW`). `DriverVersion`, `PlatformVersion`, `DeviceName` and `PlatformName` accept regular expression. Special characters, such as parenthesis, must be escaped. DPC++ runtime will select only those devices which satisfy provided values above and regex. More than one device can be specified using the piping symbol "\|".|
| `SYCL_DEVICE_ALLOWLIST` | See [below](#sycl_device_allowlist) | Filter out devices that do not match the pattern specified. `BackendName` accepts `host`, `opencl`, `level_zero`, `native_cpu` or `cuda`. `DeviceType` accepts `host`, `cpu`, `gpu`. `DeviceVendorId` accepts uint32_t in hex form (`0xXYZW`). `DriverVersion`, `PlatformVersion`, `DeviceName` and `PlatformName` accept regular expression. Special characters, such as parenthesis, must be escaped. DPC++ runtime will select only those devices which satisfy provided values above and regex. More than one device can be specified using the piping symbol "\|".|
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Note for reviewers: SYCL_DEVICE_ALLOWLIST allowed to use fpga and acc interchangeably.
I removed both. Not sure if we need to save acc.

cpu = UR_DEVICE_TYPE_CPU,
gpu = UR_DEVICE_TYPE_GPU,
accelerator = UR_DEVICE_TYPE_FPGA,
accelerator = 0x10000,
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Note for reviewers: I untied accelerator from UR_DEVICE_TYPE_FPGA and had to assign explicit value because otherwise it's value clashes with UR_DEVICE_TYPE_CPU.

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Why untie accelerator from UR_DEVICE_TYPE_FPGA? Are we removing the latter?

__SYCL_ASPECT(ext_intel_gpu_subslices_per_slice, 22)
__SYCL_ASPECT(ext_intel_gpu_eu_count_per_subslice, 23)
__SYCL_ASPECT(ext_intel_max_mem_bandwidth, 24)
__SYCL_ASPECT(ext_intel_mem_channel, 25)
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Note for reviewers: I wonder if we need to update the IDs of the aspects that follow the removed aspect.
Some of the past PRs didn't update:
#13351
So I haven't updated either.

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I think we should rework the Aspect IDs as well, but I won't mind if that's done in a separate PR.

// handles to do a cleanup later
std::vector<ur_device_handle_t> UrDevicesToCleanUp = UrDevices;

// Filter out FPGA devices since they are no longer supported.
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Note for reviewers: Currently I am filtering out all UR_DEVICE_TYPE_FPGA devices returned by UR API.
I.e. we just ignore them and don't return from platform::get_devices and everywhere else.

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I think this is not needed as FPGA devices are filtered out at UR level: #20014

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Thanks, removed this code.

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@sarnex sarnex left a comment

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esimd lgtm

@sarnex sarnex requested review from a team December 15, 2025 21:29
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@adamfidel adamfidel left a comment

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Graph change to node LGTM.

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@bader bader left a comment

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Nice clean-up. 10K lines less code to maintain. 👍

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@YuriPlyakhin YuriPlyakhin left a comment

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dpcpp-tools changes lgtm

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@uditagarwal97 uditagarwal97 left a comment

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LGTM overall

Comment on lines 165 to 170
// Transform a compile-time property list to a USM property_list (working at
// runtime). Right now only the `buffer_location<N>` has its corresponding USM
// runtime). Right there is no property that has its corresponding USM
// runtime property and is transformable
template <typename PropertyListT> inline property_list get_usm_property_list() {
if constexpr (PropertyListT::template has_property<buffer_location_key>()) {
return property_list{
sycl::ext::intel::experimental::property::usm::buffer_location(
PropertyListT::template get_property<buffer_location_key>().value)};
}
return {};
}
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I wonder if we can completely get rid of this function and all its uses? As this function just returns an empty list.

__SYCL_ASPECT(ext_intel_gpu_subslices_per_slice, 22)
__SYCL_ASPECT(ext_intel_gpu_eu_count_per_subslice, 23)
__SYCL_ASPECT(ext_intel_max_mem_bandwidth, 24)
__SYCL_ASPECT(ext_intel_mem_channel, 25)
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I think we should rework the Aspect IDs as well, but I won't mind if that's done in a separate PR.

cpu = UR_DEVICE_TYPE_CPU,
gpu = UR_DEVICE_TYPE_GPU,
accelerator = UR_DEVICE_TYPE_FPGA,
accelerator = 0x10000,
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Why untie accelerator from UR_DEVICE_TYPE_FPGA? Are we removing the latter?

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