AHB to APB Bridge – RTL Design & UVM Verification

This repository contains a synthesizable AHB to APB Bridge RTL design implemented in compliance with AMBA AHB/APB protocol specifications, along with a structured UVM-based verification environment.

The bridge performs protocol conversion between the high-performance AHB bus and the low-power APB bus, enabling efficient communication between processors and peripheral devices within an SoC architecture.

Design Highlights

RTL implementation using Verilog/SystemVerilog

FSM-based control logic for protocol conversion

AHB read and write transaction support

Proper handling of address and data phases

APB setup and enable phase generation

HREADY and HRESP response management

Modular and synthesizable architecture

Verification Methodology

UVM-based testbench architecture

Constrained random stimulus generation

Functional coverage implementation

Scoreboard-based data integrity checks

Protocol compliance verification

Project Significance

This project demonstrates:

Strong understanding of AMBA bus architecture

Practical RTL development skills

Protocol-level verification expertise

Coverage-driven verification methodology