Add RISC-V Architecture Support

[brunoproduit]

Created this issue to coordinate the implementation of RISC-V. Here's the overall idea:

1. Survey existing forks and prior art — Search for forks of lifting-bits/remill that have started RISC-V work, and check Ghidra's SLEIGH RISC-V definitions for reusable decoder/semantics work. -> it seems this commit started the work
2. Define register state and architecture skeleton — Add kArchRISCV32/kArchRISCV64 to ArchName, create State.h (x0–x31, pc, f0–f31), wire up the architecture class and factory.
3. Implement instruction decoding — Write a decoder for regular encoding formats or evaluate using SLEIGH as the decoder backend.
4. Write instruction semantics — Implement semantics for the base integer ISA (arithmetic, logic, shifts, loads/stores, branches), then extend to risc-v extensions.
5. Add tests and CI — Create tests/RISCV/ with assembly-based tests, add a cross-compilation toolchain, and integrate into CI.

[mrexodia]

Please use the official ISA tests.