[LoongArch] Strengthen stack size estimation for LSX/LASX extension

[tangaac]

This patch adds an emergency spill slot when ran out of registers.
PR #139201 introduces vstelm instructions with only 8-bit imm offset,
it causes no spill slot to store the spill registers.

[llvmbot]

@llvm/pr-subscribers-backend-loongarch

Author: None (tangaac)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/146455.diff

2 Files Affected:

• (modified) llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp (+12-1)
• (modified) llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h (+5)

diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
index 47fce37ce59f6..b3a6ca9acad63 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
@@ -29,7 +29,6 @@ using namespace llvm;
 
 #define GET_REGINFO_TARGET_DESC
 #include "LoongArchGenRegisterInfo.inc"
-
 LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode)
     : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
                                /*EHFlavor*/ 0,
@@ -254,3 +253,15 @@ bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   // reserve it.
   return MRI->canReserveReg(LoongArchABI::getBPReg());
 }
+
+bool LoongArchRegisterInfo::saveScavengerRegister(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+    MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC,
+    Register Reg) const {
+
+  DebugLoc DL;
+  const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
+  TII.copyPhysReg(MBB, I, DL, LoongArch::R12, Reg, true);
+  TII.copyPhysReg(MBB, UseMI, DL, Reg, LoongArch::R12, true);
+  return true;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
index d1e40254c2972..e9e7ee930f7f6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
@@ -52,6 +52,11 @@ struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo {
     return true;
   }
   bool canRealignStack(const MachineFunction &MF) const override;
+  bool saveScavengerRegister(MachineBasicBlock &MBB,
+                             MachineBasicBlock::iterator I,
+                             MachineBasicBlock::iterator &UseMI,
+                             const TargetRegisterClass *RC,
+                             Register Reg) const override;
 };
 } // end namespace llvm
 

[tangaac]

reduced.ll.txt
This file needs to be simplified.

[SixWeining]

Why this is changed?

[tangaac]

With this PR or not, there is no difference between debugging outputs.
So it's ok to ignore this change.

[SixWeining]

LGTM. @heiher What do you think?

[heiher]

LGTM.

[tangaac]

/cherry-pick 64a0478

[llvmbot]

/pull-request #149777