[NFC][AMDGPU] Add an IR test for v_sqrt_bf16#149629
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This was left during the upstream. Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
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@llvm/pr-subscribers-backend-amdgpu Author: Shilei Tian (shiltian) ChangesThis was left during the upstream. Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com> Full diff: https://github.com/llvm/llvm-project/pull/149629.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-math.ll b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
index 029604c2933a9..b49614d05700a 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-math.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
@@ -2,6 +2,27 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
; TODO: Add global-isel when it can support bf16
+define amdgpu_ps void @llvm_sqrt_bf16_v(ptr addrspace(1) %out, bfloat %src) {
+; GCN-LABEL: llvm_sqrt_bf16_v:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_sqrt_bf16_e32 v2, v2
+; GCN-NEXT: global_store_b16 v[0:1], v2, off
+; GCN-NEXT: s_endpgm
+ %sqrt = call bfloat @llvm.sqrt.bf16(bfloat %src)
+ store bfloat %sqrt, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_ps void @llvm_sqrt_bf16_s(ptr addrspace(1) %out, bfloat inreg %src) {
+; GCN-LABEL: llvm_sqrt_bf16_s:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_sqrt_bf16_e32 v2, s0
+; GCN-NEXT: global_store_b16 v[0:1], v2, off
+; GCN-NEXT: s_endpgm
+ %sqrt = call bfloat @llvm.sqrt.bf16(bfloat %src)
+ store bfloat %sqrt, ptr addrspace(1) %out, align 2
+ ret void
+}
define amdgpu_ps void @llvm_log2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
; GCN-LABEL: llvm_log2_bf16_v:
@@ -47,5 +68,6 @@ define amdgpu_ps void @llvm_exp2_bf16_s(ptr addrspace(1) %out, bfloat inreg %src
ret void
}
+declare bfloat @llvm.sqrt.bf16(bfloat)
declare bfloat @llvm.log2.bf16(bfloat)
declare bfloat @llvm.exp2.bf16(bfloat)
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rampitec
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Jul 21, 2025
This was referenced Jul 23, 2025
mahesh-attarde
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Jul 28, 2025
This was left during the upstream. Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
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This was left during the upstream.
Co-authored-by: Mekhanoshin, Stanislav Stanislav.Mekhanoshin@amd.com