[stm32] Place .data section into D1_SRAM instead of DTCM for H7#1048
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Could you check if the linker layout maps in the module description need to be adapted? Or were they already correct?
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The data sections were previously placed into the first memory of the contiguous section with the lowest address. The selection is changed such that the first memory of the largest contiguous ram section is used. For all supported Cortex-M devices except STM32H7 the resulting linker script will be identical. On STM32H7 .data is currently placed into the DTCM which is not accessible by peripheral DMA transfers. With the new method the D1 AXI SRAM is used for .data while .fastdata remains in the DTCM.
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I have updated the description. |
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Very good, thank you, pls merge.
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This changes the method for choosing the memory that will contain the RAM data sections. Previously the first memory of the contiguous region with the lowest address was selected. Now the first memory of the largest region will be selected instead.
On STM32H7 the
.dataand.bsssections were previously put into the DTCM which is not accessible by peripheral DMA transfers. They will now be placed into the D1 AXI SRAM with the updated selection method.For all other supported Cortex-M devices the generated linker script will be identical. All targets except STM32H7, STM32U5 and SAMD/E5x only have one contiguous region anyway and for STM32U5 and SAMD/E5x the set contains the main RAM region and additional small SRAMs.
I have verified at least one generated linker script for every linker script template and only copyright headers and white space changed.