Request access for fshaked

[fshaked]

Hi,

I'm doing research at University of Cambridge (my page).

I would like to run a suite of concurrency litmus tests on as many multi-core RISC-V SoCs as possible. This will provide essential information to validate the RISC-V memory model, and the HW itself.

Best,
Shaked Flur

[lazyparser]

Welcome! We will prepare your RISC-V machine as soon as possible. Please understand that due to the Chinese New Year holiday starting this week, all logistics and hardware preparation work may be delayed until after the holiday ends on February 24th.

[fshaked]

Thank you, and happy new year.

…

On Wed, 11 Feb 2026 at 18:12, Wei Wu ***@***.***> wrote: *lazyparser* left a comment (plctlab/riscv-lab-access#84) <#84 (comment)> Welcome! We will prepare your RISC-V machine as soon as possible. Please understand that due to the Chinese New Year holiday starting this week, all logistics and hardware preparation work may be delayed until after the holiday ends on February 24th. — Reply to this email directly, view it on GitHub <#84 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACTBFFCZYFVCNRJQ4M3K2CT4LNPGNAVCNFSM6AAAAACUTR6XLWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZTQOBVGYZTKMBTGA> . You are receiving this because you authored the thread.Message ID: ***@***.***>