Is rvx-core a single cycle processor?

[pointerliu]

Hi,

I appreciate the elegance and minimalism of rvx. I haven't run a simulation on it yet, but I'm curious about its architecture. Is rvx-core a single-cycle processor? Specifically, does it fetch an instruction and compute the result to be written to the register file within a single cycle?

Thanks! 😄

[rafaelcalcada]

Hi @pointerliu, yes, RVX is a single-cycle, unpipelined processor core. It executes one instruction per cycle, with the exception of load/store instructions, which needs 2 cycles.

[pointerliu]

Thanks ~ 😄

[VoltXd]

Hello,

I saw in a 2022 paper that RISC-V steel had 3 pipeline stages, while being able to execute one instruction per cycle. Is it still the case for RVX ? Or there is no pipeline anymore ?

[rafaelcalcada]

Hi @VoltXd, thanks for your question. RVX is a single-cycle processor core. It originated from RISC-V Steel, which had 3 pipeline stages.

The pipeline stages of RISC-V Steel didn't improve the maximum clock frequency when synthesized for FPGA, so it was removed. Removing the pipeline stages made it use less LUTs/registers when compared with the pipelined version, while keeping the same max. frequency.

[VoltXd]

Ok perfects, thank you for the informations !