ExceptionsZalrsc test generator with 92% coverage#1019
ExceptionsZalrsc test generator with 92% coverage#1019Teemooooooooo wants to merge 17 commits intoriscv:act4from
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davidharrishmc
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Many little things. Going a good direction!
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Sure. Put a add_test case just before each.
…On Thu, Mar 5, 2026 at 8:52 PM Jinghe Yu ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In generators/testgen/src/testgen/priv/extensions/ExceptionsZalrsc.py
<#1019 (comment)>
:
> + """Generate instruction address misaligned and access fault exception tests."""
+ covergroup, coverpoint = "ExceptionsZalrsc_cg", "cp_store_misaligned_priority"
+ addr_reg, data_reg, rd_reg = test_data.int_regs.get_registers(3, exclude_regs=[0])
+
+ lines = [comment_banner(coverpoint)]
+
+ lines.extend(
+ [
+ f" LA(x{addr_reg}, RVMODEL_ACCESS_FAULT_ADDRESS)",
+ f" addi x{addr_reg}, x{addr_reg}, 1",
+ f" LI(x{data_reg}, 0xDECAFCAB)", # Match original value
+ f" LI(x{rd_reg}, 0xDECAFCAB)",
+ test_data.add_testcase("sc.w_off1_priority", coverpoint, covergroup),
+ f" lr.w x{rd_reg}, (x{addr_reg})",
+ " nop",
+ write_sigupd(rd_reg, test_data),
Should I just sigupd for both .w and lr.w?
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davidharrishmc
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Good to go after minor spacing fixes and merging into the latest version.
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Could you add a comment in the coverage file by the coverpoints that aren't hit indicating why and pointing to the Sail bug, so we don't forget this and have to debug again later? |
jordancarlin
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One last comment and then this looks good to go.
| f" LI(x{data_reg}, 0xDECAFCAB)", | ||
| f" LI(x{temp_reg}, 0xBAD)", | ||
| test_data.add_testcase(f"lr.w_off{offset}", coverpoint, covergroup), | ||
| f" lr.w x{temp_reg}, (x{addr_reg})", # establish reservation | ||
| " nop", | ||
| write_sigupd(temp_reg, test_data), | ||
| f" LI(x{rd_reg}, 0xBAD)", # previous rd greater than 1 | ||
| test_data.add_testcase(f"sc.w_off{offset}", coverpoint, covergroup), | ||
| f" sc.w x{rd_reg}, x{data_reg}, (x{addr_reg})", |
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There are limits on how many instruction can be between lr.w and sc.w. To avoid conflating this test with that limit, let's move the LI(x{rd_reg}, 0xBAD) before the lr.w. So initialize all of the registers, then do the lr.w and then do the sc.w (with a nop in between). Let's also move the write_sigupd for the temp_reg after the sc.w since it should not change in between helps avoid running extra instructions between them. This applies to all sc.w/sc.d tests.
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One of the reason that I put the LI(x{rd_reg}, 0xBAD) before the sc.w is because one of the coverpoint is rd_gt_one_prev. If I move it, it would just be nop before the sc.w, should I still move it?
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Good point. We’d best keep that LI before the sc. We may have to drop the write_sigupd after the lr to prevent too much code between the two.
… On Mar 10, 2026, at 8:21 AM, Jinghe Yu ***@***.***> wrote:
@Teemooooooooo commented on this pull request.
In generators/testgen/src/testgen/priv/extensions/ExceptionsZalrsc.py <#1019 (comment)>:
> + f" LI(x{data_reg}, 0xDECAFCAB)",
+ f" LI(x{temp_reg}, 0xBAD)",
+ test_data.add_testcase(f"lr.w_off{offset}", coverpoint, covergroup),
+ f" lr.w x{temp_reg}, (x{addr_reg})", # establish reservation
+ " nop",
+ write_sigupd(temp_reg, test_data),
+ f" LI(x{rd_reg}, 0xBAD)", # previous rd greater than 1
+ test_data.add_testcase(f"sc.w_off{offset}", coverpoint, covergroup),
+ f" sc.w x{rd_reg}, x{data_reg}, (x{addr_reg})",
One of the reason that I put the LI(x{rd_reg}, 0xBAD) before the sc.w is because one of the coverpoint is rd_gt_one_prev. If I move it, it would just be nop before the sc.w, should I still move it?
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ExceptionsZalrsc python test generator at 92% coverage
Note that illegal sc.w does not get coverage as SAIL stores content in by bytes instead of giving exceptions
Sail issue: Misaligned sc.w does not trigger store-address-misaligned exception sail-riscv#1574
Note that QEMU also has a bug where sc instructions at illegal address do not trigger access fault exception
QEMU issue: https://gitlab.com/qemu-project/qemu/-/issues/3323
_generate_store_address_misaligned_tests is not hitting the following coverpoints due to SAIL bug
Cross cp_store_address_misaligned_illegal_w
Cross cp_store_address_misaligned_illegal_d