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| # MTVEC (Section 4 — mtvec WARL) | ||
| MTVEC_MODES: [0, 1] # VERIFIED — control_status_registers.rst:589 "both direct and vectored supported" | ||
| MTVEC_ACCESS: rw # VERIFIED — control_status_registers.rst:577 MODE[0] is RW | ||
| MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain # ASSUMED — standard trap vector behavior |
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Are there any illegal values in MTVEC? Worth looking at the RTL on this one.
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I will try to confirm assumed values that is my next task for completion of this draft.
jordancarlin
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Mar 3, 2026
Configuration for CV32E40P core (Phase 1 CTP research) with all parameters documented and verified against manual. Baseline configuration: COREV_PULP=0, FPU=0, NUM_MHPMCOUNTERS=1 ISA Extensions: - Base: I, M, C - Standard: Zca, Zicsr, Zifencei, Zicntr - Supervisor: Sm, Smhpm Parameters: 44 documented with verification status - 21 VERIFIED (with manual citations) - 7 FROM MANUAL - 13 ASSUMED (reasonable defaults) - 2 QUESTIONABLE (flagged for review) - 1 UNKNOWN Research notes and atomic concepts in separate Obsidian vault.
CV32E40P configuration updates based on detailed RTL source code investigation: Key Changes: - Removed C extension from implemented_extensions (C = Zca + floating-point, FPU=0 means only Zca) - TRAP_ON_UNIMPLEMENTED_CSR: Updated from false to true * RTL cv32e40p_decoder.sv line 2978 has 'default : csr_illegal = 1'b1' * Any CSR not in decoder whitelist causes IllegalInstruction exception * Config assumption (silent 0 return) contradicts actual RTL behavior - TRAP_ON_ILLEGAL_WLRL: Verified false (no changes needed) * Decoder (ID stage) validates CSR addresses, not write data values * Write data only available at EX stage (too late for trap) * cs_registers.sv silently masks WLRL field writes (lines 954-1023) * Architecture constraint: masking is only viable option - Commented out incomplete parameters (MTVAL, misaligned, IDs, MTVEC, Sm, HPM) Investigation Sources: - CV32E40P manual: intro.rst, control_status_registers.rst, exceptions_interrupts.rst - RISC-V Unified DB: extension definitions, parameter schemas - CV32E40P RTL: decoder.sv (CSR validation), cs_registers.sv (field masking)
NUM_PMP_ENTRIES is defined by Smpmp extension which CV32E40P does not implement; remove it. Add TIME_CSR_IMPLEMENTED: false (defined by Zicntr, which CV32E40P does implement); verified via perf_counters.rst:130-133.
Add F extension (v2.2.0) to implemented_extensions. Update description to RV32IMCF. Update IMP_ID_VALUE 0x0->0x1 (cs_registers.sv:511-513: FPU==1 sets mimpid=0x1). Add MUTABLE_MISA_F: false (F bit is RO, control_status_registers.rst:1444,1457). Add HW_MSTATUS_FS_DIRTY_UPDATE: imprecise and MSTATUS_FS_LEGAL_VALUES: [0,1,2,3] (cs_registers.sv:964,1034; control_status_registers.rst:448-456,483).
… RV32IMC (FPU=0) config Move cv32e40p.yaml into cv32e40p_v1.8.3_rv32imcf/ subfolder and rename to match versioned naming convention (core/version-variant/file). Follows same structure as cve2 and cvw configs. Add cv32e40p_v1.8.3_rv32imc.yaml (FPU=0, mimpid=0) recovered from git history as the baseline RV32IMC certified configuration (RTL Freeze v1.8.3, mimpid=0).
Add two architecture configuration yamls for CV32E40P v1.0.0 (RTL Freeze 2020-12-10): - cv32e40p_v1.0.0_rv32imc: FPU=0 baseline, the only certified/frozen config for v1.0.0 (mimpid=0, events 0-10 only) - cv32e40p_v1.0.0_rv32imcf: FPU=1 path for completeness (not RTL-frozen in v1.0.0) Key differences vs v1.8.3 FPU=1: mimpid always 0x0 (hardwired), mstatus.FS not implemented (bits[16:13] hardwired 0, MSTATUS_FS_LEGAL_VALUES=[0]), HPM events 12-15 active via internal APU dispatcher (cv32e40p_core.sv APU localparam).
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Configuration for CV32E40P core (Phase 1 CTP research) with all parameters documented and verified against manual.
Baseline configuration: COREV_PULP=0, FPU=0, NUM_MHPMCOUNTERS=1
ISA Extensions:
Parameters: 44 documented with verification status
Research notes and atomic concepts in separate Obsidian vault.