optoe: Add CMIS Bank support for transceivers with >8 lanes#473
optoe: Add CMIS Bank support for transceivers with >8 lanes#473ishidawataru wants to merge 9 commits intosonic-net:masterfrom
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@prgeor PTAL |
| + * 2 byte writes are acceptable for PE and Vout changes per | ||
| + * Application Note AN-2071. | ||
| + * | ||
| + * use 2 bytes for CMIS devices since CMIS 5.3 requires write both BankSelect and PageSlect in one WRITE acess. |
| - The default bank size is set to 4, and can be modified via the 'bank_size' sysfs entry. | ||
| - For 'optoe3', the 'write_max' value is updated to 2 to comply with CMIS requirements, | ||
| which mandate that both bank and page values be updated in a single WRITE operation. | ||
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It’d be great if you could add a paragraph how to verify/test this to the commit message too.
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@prgeor I updated the patch based on our discussion PTAL. |
@ishidawataru Ack. reviewing. |
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@ishidawataru can you define what do you mean by |
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For example, if I also added a commit that explains this in the comment. |
| /* fundamental unit of addressing for EEPROM */ | ||
| #define OPTOE_PAGE_SIZE 128 | ||
| + | ||
| +#define OPTOE_DEFAULT_BANK_SIZE 0 |
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@ishidawataru the default bank is 0, which means modules that support 8 lanes, the bank size = 1?
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@ishidawataru This probably can be removed if we implement full range of linear address for all bank pages. See my comments below
| +#define OPTOE_MAX_SUPPORTED_BANK_SIZE 8 | ||
| +#define OPTOE_NON_BANKED_PAGE_SIZE 16 /* page 00h-0Fh are not banked */ | ||
| +#define OPTOE_BANKED_PAGE_SIZE 240 /* page 10h-FFh are banked */ |
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@ishidawataru I am bit confused with respect to naming these by _SIZE. From the code use, it looks like these should be _COUNT?
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If these constants are still necessary after the discussion below, I’ll rename them as you suggested.
| + * For CMIS transceivers that support Banked Pages, access to these pages | ||
| + * is also supported. To access the banked pages, set the number of banks | ||
| + * to access via the `bank_size` sysfs entry. | ||
| + * By default, `bank_size` is set to 0, which disables this feature. |
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@ishidawataru We probably don't need this. see my comments above.
| + * For just a Page Index change (mapping another Page in the current Bank), | ||
| + * or for mapping an arbitrary unbanked Page to Upper Memory, a host may WRITE only the PageSelect Byte. | ||
| + */ | ||
| + if (bank > 0) { |
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@ishidawataru would it be good to have the sanity check to validate the bank value to what the module supports? Page 01h, Byte 142
| + return count; | ||
| +} | ||
| + | ||
| +static ssize_t set_bank_size(struct device *dev, |
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@ishidawataru do we need this? What is the usecase? I thought the number of banks is already advertised so the optoe driver can read the advertisement and cache the value? Are you considering a case where the module is swapped?
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Pull request overview
This pull request adds CMIS Bank support to the optoe3 driver to enable access to CMIS transceivers with more than 8 lanes (e.g., OSFP-XD, CPO OEs). The implementation adds a configurable bank_size sysfs interface that allows extending the addressable EEPROM space beyond the default single bank (256 pages) to support up to 8 banks, mapping them into a linear address space.
Changes:
- Adds bank register handling logic to the optoe driver for CMIS transceivers (optoe3 device class)
- Implements
bank_sizesysfs attribute to enable/configure bank support (defaults to 0 = disabled) - Updates address translation logic to compute bank, page, and offset from linear address space
- Modifies page/bank register restoration logic to handle bank select register writes
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 9 comments.
| File | Description |
|---|---|
| patches-sonic/series | Adds the new bank support patch to the patch series, positioned correctly after existing optoe patches |
| patches-sonic/driver-support-optoe-bank-support.patch | Complete implementation of CMIS bank support including address translation, register handling, sysfs interface, and memory size calculations |
| + * Memory layout: multiple banks, each containing 256 pages of 128 bytes. | ||
| + */ | ||
| + loff_t offset_in_paged_area = *offset - OPTOE_PAGE_SIZE; | ||
| + const size_t bytes_per_bank = OPTOE_ARCH_PAGES * OPTOE_PAGE_SIZE; // 256 * 128 = 32KB |
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Use C-style comment syntax /* / instead of C++ style //. Kernel code should use C-style comments for inline code comments. The comment should be: / 256 * 128 = 32KB */
| + const size_t bytes_per_bank = OPTOE_ARCH_PAGES * OPTOE_PAGE_SIZE; // 256 * 128 = 32KB | |
| + const size_t bytes_per_bank = OPTOE_ARCH_PAGES * OPTOE_PAGE_SIZE; /* 256 * 128 = 32KB */ |
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@bobby-nexthop can you review? |
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Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
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Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Signed-off-by: Wataru Ishida <wataru.ishid@gmail.com>
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@prgeor all CI checks have passed. PTAL |
| + * The maximum supported bank size in this version is 8. | ||
| + */ | ||
| +#define OPTOE_DEFAULT_BANK_SIZE 0 | ||
| +#define OPTOE_MAX_SUPPORTED_BANK_SIZE 8 |
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@ishidawataru Why the value is 8? As per CMIS spec, the max number of lanes is 32 which means MAX bank size is 4

This patch adds CMIS Bank support to the 'optoe3' device class in order
to enable access to CMIS transceivers with more than 8 lanes (e.g., OSFP-XD, CPO OEs).
The default bank size is set to 4, and can be modified via the 'bank_size' sysfs entry.For 'optoe3', the 'write_max' value is updated to 2 to comply with CMIS requirements,which mandate that both bank and page values be updated in a single WRITE operation.
Updated the behavior as below after discussing with @prgeor offline
automatically updated to 2 to comply with CMIS requirements,
which mandate that both bank and page values be updated in a single WRITE operation.
Only tested with the SONiC VM + i2c-stub.
Snip of dmesg. See bank:3 is accessed.
Not tested with real hardware yet.