Timing violation on Tang Nano 9K?

[rhgndf]

I keep getting wrong frame magics:

Frame magic: D676C5DC, framecounter: 01B5, pack_state: 00
Frame magic: AA7AC7B1, framecounter: 71D6, pack_state: 00
Frame magic: AA7AC7B1, framecounter: 71D6, pack_state: 00
Frame magic: DA1ACAB1, framecounter: 71B7, pack_state: 00
Frame magic: DA1ACAB1, framecounter: 71B7, pack_state: 00
Frame magic: 7CD0A011, framecounter: 7178, pack_state: 00
Frame magic: 7CD0A011, framecounter: 7178, pack_state: 00
Frame magic: C67DC6B1, framecounter: 01B9, pack_state: 00
Frame magic: C67DC6B1, framecounter: 01B9, pack_state: 00
Frame magic: DA7ACDD1, framecounter: 712A, pack_state: 00
Frame magic: DA7ACDD1, framecounter: 712A, pack_state: 00
Frame magic: DB7ACAB1, framecounter: C1BB, pack_state: E0
Frame magic: DB7ACAB1, framecounter: C1BB, pack_state: E0
Frame magic: 5A1AC011, framecounter: 076C, pack_state: 00
Frame magic: 5A1AC011, framecounter: 076C, pack_state: 00
Frame magic: BFB0CDB7, framecounter: 01BD, pack_state: 00
Frame magic: BFB0CDB7, framecounter: 01BD, pack_state: 00
Frame magic: BAEAC6C1, framecounter: 01A2, pack_state: C0
Frame magic: BAEAC6C1, framecounter: 01A2, pack_state: C0
Frame magic: BA7ACAB1, framecounter: 01BF, pack_state: 05
Frame magic: ABDAACB1, framecounter: F1C0, pack_state: 00
Frame magic: ABDAACB1, framecounter: F1C0, pack_state: 00
Frame magic: DA7ACAB1, framecounter: 01C1, pack_state: A9

The place and route also reports timing violations?

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	data_pll/CLKOUT.default_gen_clk	50.996(MHz)	122.724(MHz)	4	TOP
2	div_5/CLKOUT.default_gen_clk	67.495(MHz)	45.834(MHz)	16	TOP

Any idea how to resolve this?

[rhgndf]

These values, along with enabling the 'open source' fifo gives 0 counter errors.

localparam HDMI_PLL_IDIV  = 0;
localparam HDMI_PLL_FBDIV = 7;
localparam HDMI_PLL_ODIV  = 4;

localparam DATA_PLL_IDIV  = 8;
localparam DATA_PLL_FBDIV = 10;
localparam DATA_PLL_ODIV  = 32;

[steve-m]

Yes, the Tang Nano 9K is the most tricky one due to the speed grade of the FPGA.
After I recently found a pipelined TMDS encoder optimized for the Gowin FPGAs, I switched to it with commit a9bc725. Now Fmax for the div_5 clock is 76.648 MHz.

Can you retry your test?