When running iverilog on the following program:
module module_0 #(
parameter id_1 = 32'd92,
parameter id_3 = 32'd50,
parameter id_4 = 32'd25,
parameter id_8 = 32'd99,
parameter id_9 = 32'd40
) ();
case ((1))
1: begin
if (id_3) begin
else begin
end else begin
if (1)
id_3 = id_9[1];
end
end
end
endcase
assign id_8 = 1;
endmoduleiverilog outputs the following:
test656.v:16: error: Invalid module item.
test656.v:20: syntax error
test656.v:22: error: Invalid module item.
test656.v:2: assert: pform.cc:1478: failed assertion lexical_scope == cur_module
Aborted
I'm using this Icarus Verilog version:
Icarus Verilog version 13.0 (devel) (s20221226-526-g5cbdff202)
When running
iverilogon the following program:iverilog outputs the following:
I'm using this Icarus Verilog version:
Icarus Verilog version 13.0 (devel) (s20221226-526-g5cbdff202)