Is your feature request related to a problem? Please describe.
Since Charlib knows the logic function of the cell being characterized,
and also recognizes all the timing arcs and timing checks, it has all
the information needed to generate a Verilog model of the standard
cell library being characterized including specify block with IO path
delays and timing checks.
Is your feature request related to a problem? Please describe.
Since Charlib knows the logic function of the cell being characterized,
and also recognizes all the timing arcs and timing checks, it has all
the information needed to generate a Verilog model of the standard
cell library being characterized including specify block with IO path
delays and timing checks.