TSI/FESVR memory loading failure - PutPartial Assertaion failed #2308
Description
Background Work
- Yes, I searched the mailing list
- Yes, I searched prior issues
- Yes, I searched the documentation
Chipyard Version and Hash
Release: 1.5.0
Hash: a6a6a6
OS Setup
Ex: Output of uname -a + lsb_release -a + printenv + conda list
Other Setup
Ex: Prior steps taken / Documentation Followed / etc...
Current Behavior
I am trying to load a custom .elf file (pretty big) into a TLRAM/scratchpad using TSI/FESVR, and this problem showed up:
I checked the .out file in verilator/output and it is blank
Expected Behavior
It should load like other .elf files
Other Information
No response