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CharanK-glitch/README.md

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💫 About Me:

🔭 I’m currently working on Hardware Security
💬 Ask me about Cryptography, PQC, Hardware Security, Side channel Attacks, RTL-GDSII Design
📫 How to reach me kashmahanticharan@gmail.com

🌐 Socials:

Instagram LinkedIn email

💻 Tech Stack:

C C++ Python Netlify Anaconda MySQL Keras Matplotlib mlflow TensorFlow Pandas NumPy PyTorch scikit-learn Scipy Git GitHub Arduino Cisco CMake Docker Notion C C++ mlflow Cisco CMake Scala

📊 GitHub Stats:



🏆 GitHub Trophies

🔝 Top Contributed Repo


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  1. RV32I RV32I Public

    Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applicat…

    Verilog 5 1

  2. ARM-Verilog- ARM-Verilog- Public

    A lightweight ARM-compatible processor core implementing the ARMv6-M architecture with basic peripherals, designed for embedded applications.

    Verilog 1

  3. picorv32 picorv32 Public

    Forked from YosysHQ/picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog 1

  4. PoMMES PoMMES Public

    Forked from ChairImpSec/PoMMES

    PoMMES: Prevention of Micro-architectural Leakages in Masked Embedded Software

    C++ 1

  5. riscv-gnu-toolchain riscv-gnu-toolchain Public

    Forked from riscv-collab/riscv-gnu-toolchain

    GNU toolchain for RISC-V, including GCC

    C