ARM Cortex-M Style Minimal Core

Overview

A lightweight ARM-compatible processor core implementing the ARMv6-M architecture with basic peripherals, designed for embedded applications.

Core Features

• Pipeline: 3-stage (Fetch-Decode-Execute)
• ISA Support:
  • Thumb-2 subset (16/32-bit mixed)
  • Base ARMv6-M instructions
• Clock Speed: 50 MHz (synthesized)
• Memory Bus: 32-bit AHB-Lite

Peripherals

Peripheral	Base Address	Features
GPIO	0x40000000	16 I/O pins, interrupt capability
UART	0x40001000	115200 baud, FIFO buffered
SysTick Timer	0xE000E010	24-bit downcounter, interrupt
NVIC	0xE000E100	32 interrupt vectors

Memory Map

0x00000000 - 0x1FFFFFFF : Flash (32MB)
0x20000000 - 0x3FFFFFFF : SRAM (32MB) 
0x40000000 - 0x5FFFFFFF : Peripherals
0xE0000000 - 0xE00FFFFF : System Control